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path: root/trunk/darwin/firmware/PIC/sim/master.stc
blob: 93db575ecdf58136357536ec15f08060fec1ce46 (plain) 
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load c usart.stim
node testnode
attach test1 testnode portb7

#node test_rx
#attach test_rx rx1 portb1
#node test_tx
#attach test_tx portb2
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-14 22:15:37 +0000