Simple 6 x 8 bit EPP driven I/O port configuration register map


REGISTER	ADDRESS		FUNCTION	

IDCOOKIE0	0x00		CHECK CONFIG =0xFE
IDCOOKIE1	0x01		CHECK CONFIG =0xCA
IDCOOKIE2	0x02		CHECK CONFIG =0xAA
IDCOOKIE3	0x03		CHECK CONFIG =0x55

CONFIGNAME0	0x04		'E'
CONFIGNAME1	0x05		'P'
CONFIGNAME2	0x06		'P'
CONFIGNAME3	0x07		'I'
CONFIGNAME4	0x08		'O'
CONFIGNAME5	0x09		'8'
CONFIGNAME6	0x0A		'-'
CONFIGNAME7	0x0B		'2' or '4' depending on FPGA

VERSION0	0x0C		Version
VERSION1	0x0D
VERSION2	0x0E
VERSION3	0x0F

PORT0		0x10		PORT0 DATA (IOBITS 0..7)
PORT1		0x11		PORT0 DATA (IOBITS 8..15)
PORT2		0x12		PORT0 DATA (IOBITS 16..23)
PORT3		0x13		PORT0 DATA (IOBITS 24..31)
PORT4		0x14		PORT0 DATA (IOBITS 32..39)
PORT5		0x15		PORT0 DATA (IOBITS 40..47)

Six byte wide GPIO ports, each I/O bit can be input or output 
depending on cooresponding DDR registers:

PORT0DDR	0x20		PORT0 DATA DIRECTION REGISTER (1 = OUT)
PORT1DDR	0x21		PORT1 DATA DIRECTION REGISTER (1 = OUT)
PORT2DDR	0x22		PORT2 DATA DIRECTION REGISTER (1 = OUT)
PORT3DDR	0x23		PORT3 DATA DIRECTION REGISTER (1 = OUT)
PORT4DDR	0x24		PORT4 DATA DIRECTION REGISTER (1 = OUT)
PORT5DDR	0x25		PORT5 DATA DIRECTION REGISTER (1 = OUT)

A '1' bit in a DDR register sets the cooresponding bit in the data port
to output mode. Inputs always read the I/O pin status even in output mode.
All pins configured as inputs when FPGA is first configured (DDR registers
initialized to 0x00)

SPICS		0x7D		BIT 0 CONTROLS EEPROM /CS PIN
SPIDATA		0x7E		WRITE SHIFTS 8 BITS TO EEPROM
				READS READ SHIFT REGISTER

RECONFIG	0x7F		WRITING 0x5A HERE RESETS FPGA


NOTE: Addresses with A7 high enable address autoinc feature. 
      I/O devices ignore A7 so for example you can write all 6 
      I/O ports with this sequence:

      WriteAddress(0x90)         ; address of PORT0 with A7 high
      WriteData(Port0Data)
      WriteData(Port1Data)
      WriteData(Port2Data)
      WriteData(Port3Data)
      WriteData(Port4Data)
      WriteData(Port5Data)