7I43 INTERFACE CONNECTIONS

SIGNAL			PIN 	FUNCTION
CLK			53	50 MHZ CLOCK
                                            
EPP/USBDATABUS0		68	EPP/USB BI-DIRECTIONAL DATA			
EPP/USBDATABUS1		63	""
EPP/USBDATABUS2		60	""
EPP/USBDATABUS3		59	""
EPP/USBDATABUS4		51	""
EPP/USBDATABUS5		50	""
EPP/USBDATABUS6		47	""
EPP/USBDATABUS7		46	""

USB_RD			55	ACTIVE LOW OUT = USB FIFO READ STROBE			
USB_WRITE		56	ACTIVE LOW OUT = USB FIFO WRITE STROBE
USB_RXF			69	ACTIVE LOW IN = RXFIFO HAS DATA STATUS
USB_TXE			83	ACTIVE LOW IN = TXFIFO HAS SPACE STATUS						   
(USB_TXE was 57 on proto)

EPP_READ		84	INPUT = HIGH FOR READ/LOW FOR WRITE
EPP_DSTROBE		79      ACTIVE LOW INPUT = DATA STROBE
EPP_ASTROBE		80	ACTIVE LOW INPUT = ADDRESS STROBE
EPP_WAIT		82	HANDSHAKE SIGNAL

SPICLK			70	OUT, SPI CLOCK
SPICS			78      ACTIVE LOW OUT = SPI CHIP SELECT
SPIIN			76	IN, CONNECTS TO EEPROM SPIOUT	
SPIOUT			77	OUT, CONNECTS TO EEPROM SPIIN 

PARACONFIG		40	OUT, TELLS CPLD FPGA MODE, 1=EPP,0=USB

RECONFIG		52	OUT, SET LOW TO ASSERT /PROGRAM FOR RECONFIG