Configuration Name: HOSTMOT2 General configuration information: BoardName : MESA7I43 FPGA Size: 400 KGates FPGA Pins: 144 Number of IO Ports: 2 Width of one I/O port: 24 Clock Low frequency: 50.0000 MHz Clock High frequency: 100.0000 MHz Modules in configuration: Module: WatchDog There are 1 of WatchDog in configuration Version: 0 Registers: 3 BaseAddress: 0C00 ClockFrequency: 50.000 MHz Module: IOPort There are 2 of IOPort in configuration Version: 0 Registers: 5 BaseAddress: 1000 ClockFrequency: 50.000 MHz Module: QCount There are 4 of QCount in configuration Version: 2 Registers: 5 BaseAddress: 3000 ClockFrequency: 50.000 MHz Module: PWM There are 4 of PWM in configuration Version: 0 Registers: 5 BaseAddress: 4000 ClockFrequency: 100.000 MHz Module: StepGen There are 6 of StepGen in configuration Version: 0 Registers: 10 BaseAddress: 2000 ClockFrequency: 50.000 MHz Module: AddrX There are 1 of AddrX in configuration Version: 0 Registers: 4 BaseAddress: 7800 ClockFrequency: 50.000 MHz Module: LED There are 1 of LED in configuration Version: 0 Registers: 1 BaseAddress: 0200 ClockFrequency: 50.000 MHz Configuration pin-out: IO Connections for P4 Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir 1 0 IOPort QCount 1 Quad-B (In) 3 1 IOPort QCount 1 Quad-A (In) 5 2 IOPort QCount 0 Quad-B (In) 7 3 IOPort QCount 0 Quad-A (In) 9 4 IOPort QCount 1 Quad-IDX (In) 11 5 IOPort QCount 0 Quad-IDX (In) 13 6 IOPort PWM 1 PWM (Out) 15 7 IOPort PWM 0 PWM (Out) 17 8 IOPort PWM 1 Dir (Out) 19 9 IOPort PWM 0 Dir (Out) 21 10 IOPort PWM 1 /Enable (Out) 23 11 IOPort PWM 0 /Enable (Out) 25 12 IOPort QCount 3 Quad-B (In) 27 13 IOPort QCount 3 Quad-A (In) 29 14 IOPort QCount 2 Quad-B (In) 31 15 IOPort QCount 2 Quad-A (In) 33 16 IOPort QCount 3 Quad-IDX (In) 35 17 IOPort QCount 2 Quad-IDX (In) 37 18 IOPort PWM 3 PWM (Out) 39 19 IOPort PWM 2 PWM (Out) 41 20 IOPort PWM 3 Dir (Out) 43 21 IOPort PWM 2 Dir (Out) 45 22 IOPort PWM 3 /Enable (Out) 47 23 IOPort PWM 2 /Enable (Out) IO Connections for P3 Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir 1 24 IOPort StepGen 0 Step/Table1 (Out) 3 25 IOPort StepGen 0 Dir/Table2 (Out) 5 26 IOPort StepGen 0 Table3 (Out) 7 27 IOPort StepGen 0 Table4 (Out) 9 28 IOPort StepGen 1 Step/Table1 (Out) 11 29 IOPort StepGen 1 Dir/Table2 (Out) 13 30 IOPort StepGen 1 Table3 (Out) 15 31 IOPort StepGen 1 Table4 (Out) 17 32 IOPort StepGen 2 Step/Table1 (Out) 19 33 IOPort StepGen 2 Dir/Table2 (Out) 21 34 IOPort StepGen 2 Table3 (Out) 23 35 IOPort StepGen 2 Table4 (Out) 25 36 IOPort StepGen 3 Step/Table1 (Out) 27 37 IOPort StepGen 3 Dir/Table2 (Out) 29 38 IOPort StepGen 3 Table3 (Out) 31 39 IOPort StepGen 3 Table4 (Out) 33 40 IOPort StepGen 4 Step/Table1 (Out) 35 41 IOPort StepGen 4 Dir/Table2 (Out) 37 42 IOPort StepGen 4 Table3 (Out) 39 43 IOPort StepGen 4 Table4 (Out) 41 44 IOPort StepGen 5 Step/Table1 (Out) 43 45 IOPort StepGen 5 Dir/Table2 (Out) 45 46 IOPort StepGen 5 Table3 (Out) 47 47 IOPort StepGen 5 Table4 (Out)