##############################################
#      BASIC UCF SYNTAX EXAMPLES V2.1.5      #
##############################################
#
#              TIMING SPECIFICATIONS
#
# Timing specifications can be applied to the entire device (global) or to
# specific groups of login in your PLD design (called "time groups').
# The time groups are declared in two basic ways.
#
# Method 1: Based on a net name, where 'my_net' is a net that touchs all the
#           logic to be grouped in to 'logic_grp'. Example:
#NET my_net TNM_NET = logic_grp
#
# Method 2: Group uing the key word 'TIMEGRP' and declare using the names of
#           logic in your design. Example:
#TIMEGRP group_name = FFS ("U1/*")
#           creates a group called 'group_name' for all flip-flops with in
#           the hierarchical block called U1. Wildcards are valid.
#
# Grouping is very importadatant because it lets you tell the software which parts
# of a design run at which speeds.  For the majority of the designs with only
# one clock the very simple global constraINTs.
#
# The type of grouping constraINT you use can vary depending on the synthesis
# tools you are using.  For example, Synplicity does well with Method 1, while
# FPGA Express does beter with Method 2.
#
#
############################################################
# INTernal to the device clock speed specifications - Tsys #
############################################################
#
# data      _________      /^^^^^\       _________   out
# ----------| D   Q |-----{ LOGIC } -----| D   Q |------
#           |       |      \vvvvv/       |       |
#        ---|> CLK  |                 ---|> CLK  |
# clock  |  ---------                 |  ---------
# ------------------------------------
#
# ---------------
# Single Clock
# ---------------
#
# ----------------
# PERIOD TIME-SPEC
# ----------------
# The PERIOD spec. covers all timing paths that start or end at a
# register, latch, or synchronous RAM which are clocked by the reference
# net (excluding pad destinations).  Also covered is the setup
# requirement of the synchronous element relative to other elements
# (ex. flip flops, pADS, etc...).
# NOTE:  The default unit for time is nanoseconds.
#
#NET clock PERIOD = 50ns
#
#       -OR-
#
# ------------------
# FROM:TO TIME-SPECs
# ------------------
# FROM:TO style timespecs can be used to constrain paths between time
# groups.  NOTE:  Keywords:  RAMS, FFS, PADS, and LATCHES are predefined
# time groups used to specify all elements of each type in a design.
#TIMEGRP RFFS = RISING FFS ("*");  // creates a rising group called RFFS
#TIMEGRP FFFS = FALLING FFS ("*");  // creates a falling group called FFFS
#TIMESPEC TSF2F  = FROM : FFS   : TO : FFS   : 50 ns; // Flip-flips with the same edge
#TIMESPEC TSR2F  = FROM : RFFS  : TO : FFFS  : 25 ns; // rising edge to falling edge
#TIMESPEC TSF2R  = FROM : FFFS  : TO : RFFS  : 25 ns; // falling edge to rising edge
#
# ---------------
# Multiple Clocks
# ---------------
# Requires a combination of the 'Period' and 'FROM:TO' type time specifications
#NET clock1 TNM_NET = clk1_grp
#NET clock2 TNM_NET = clk2_grp
#
#TIMESPEC TS_clk1 = PERIOD : clk1_grp : 50
#TIMESPEC TS_clk2 = PERIOD : clk2_grp : 30
#TIMESPEC TS_ck1_2_ck2 = FROM : clk1_grp : TO : clk2_grp : 50
#TIMESPEC TS_ck2_2_ck1 = FROM : clk2_grp : TO : clk1_grp : 30
#
#
############################################################
# CLOCK TO OUT specifications - Tco                        #
############################################################
#
# from      _________      /^^^^^\       --------\
# ----------| D   Q |-----{ LOGIC } -----| Pad    >
# PLD       |       |      \vvvvv/       --------/
#        ---|> CLK  |
# clock  |  ---------
# --------
#
# ----------------
# OFFSET TIME-SPEC
# ----------------
# To automatically include clock buffer/routing delay in your
# clock-to-out timing specifications, use OFFSET constraINTs .
# For an output where the maximum clock-to-out (Tco) is 25 ns:
#NET out_net_name OFFSET = OUT 25 AFTER clock_net_name
#
#      -OR-
#
# ------------------
# FROM:TO TIME-SPECs
# ------------------
#TIMESPEC TSF2P  = FROM : FFS   : TO : PADS  : 25 ns
# Note that FROM: FFS : TO: PADS constraINTs start the delay analysis
# at the flip flop itself, and not the clock input pin.  The recommended
# method to create a clock-to-out constraINT is to use an OFFSET constraINT.
#
#
############################################################
# Pad to Flip-Flop speed specifications - Tsu              #
############################################################
#
# ------\         /^^^^^\       _________   INTo PLD
# |pad   >-------{ LOGIC } -----| D   Q |------
# ------/         \vvvvv/       |       |
#                            ---|> CLK  |
# clock                      |  ---------
# ----------------------------
#
# ----------------
# OFFSET TIME-SPEC
# ----------------
# To automatically account for clock delay in your input setup timing
# specifications, use OFFSET constraINTs.
# For an input where the maximum setup time is 25 ns:
#NET in_net_name OFFSET = IN 25 BEFORE clock_net_name
#
#      -OR-
#
# ------------------
# FROM:TO TIME-SPECs
# ------------------
#TIMESPEC TSP2F  = FROM : PADS  : TO : FFS   : 25 ns
# Note that FROM: PADS : TO: FFS constraINTs do not take INTo account any
# delay for the clock path.  The recommended method to create an input
# setup time constraINT is to use an OFFSET constraINT.
#
#
############################################################
# Pad to Pad speed specifications - Tpd                    #
############################################################
#
# ------\         /^^^^^\       -------\
# |pad   >-------{ LOGIC } -----| pad   >
# ------/         \vvvvv/       -------/
#
# ------------------
# FROM:TO TIME-SPECs
# ------------------
#TIMESPEC TSP2P  = FROM : PADS  : TO : PADS  : 125 ns
#
#
############################################################
# Other timing specifications                              #
############################################################
#
# -------------
# TIMING IGNORE
# -------------
# If you can ignore timing of paths, use Timing Ignore (TIG). NOTE: The
# "*" character is a wild-card which can be used for bus names.  A "?"
# character can be used to wild-card one character.
# Ignore timing of net reset_n:
#NET : reset_n : TIG
#
# Ignore data_reg(7:0) net in instance mux_mem:
#NET : mux_mem/data_reg* : TIG
#
# Ignore data_reg(7:0) net in instance mux_mem as related to a TIMESPEC
# named TS01 only:
#NET : mux_mem/data_reg* : TIG = TS01
#
# Ignore data1_sig and data2_sig nets:
#NET : data?_sig : TIG
#
# ---------------
# PATH EXCEPTIONS
# ---------------
# If your design has outputs that can be slower than others, you can
# create specific timespecs similar to this example for output nets
# named out_data(7:0) and irq_n:
#TIMEGRP slow_outs = PADS(out_data* : irq_n)
#TIMEGRP fast_outs = PADS : EXCEPT : slow_outs
#TIMESPEC TS08 = FROM : FFS : TO : fast_outs : 22
#TIMESPEC TS09 = FROM : FFS : TO : slow_outs : 75
#
# If you have multi-cycle FF to FF paths, you can create a time group
# using either the TIMEGRP or TNM statements.
#
# WARNING:  Many VHDL/verilog synthesizers do not predictably name flip
# flop Q output nets.  Most synthesizers do assign predictable instance
# names to flip flops, however.
#
# TIMEGRP example:
#TIMEGRP slowffs = FFS(inst_path/ff_q_output_net1* :
#inst_path/ff_q_output_net2*)
#
# TNM attached to instance example:
#INST inst_path/ff_instance_name1_reg* TNM = slowffs
#INST inst_path/ff_instance_name2_reg* TNM = slowffs
#
# If a FF clock-Enable is used on all flip flops of a multi-cycle path,
# you can attach TNM to the clock Enable net.  NOTE:  TNM attached to a
# net "forward traces" to any FF, LATCH, RAM, or PAD attached to the
# net.
#NET ff_clock_Enable_net TNM = slowffs
#
# Example of using "slowffs" timegroup, in a FROM:TO timespec, with
# either of the three timegroup methods shown above:
#TIMESPEC TS10 = FROM : slowffs : TO : FFS : 100
#
# Constrain the skew or delay associate with a net.
#NET any_net_name MAXSKEW = 7
#NET any_net_name MAXDELAY = 20 ns
#
#
# ConstraINT priority in your .ucf file is as follows:
#
#    highest 1.  Timing Ignore (TIG)
#                 2.  FROM : THRU : TO specs
#             3.  FROM : TO specs
#    lowest  4.  PERIOD specs
#
# See the on-line "Library Reference Guide" document for
# additional timespec features and more information.
#
#
############################################################
#                                                                                                                    #
#         LOCATION and ATTRIBUTE SPECIFICATIONS                        #
#                                                                                                                    #
############################################################
# Pin and CLB location locking constraINTs                 #
############################################################
#
# -----------------------
# Assign an IO pin number
# -----------------------
#INST io_buf_instance_name  LOC = P110
#NET io_net_name  LOC = P111
#
# -----------------------
# Assign a signal to a range of I/O pins
# -----------------------
#NET "signal_name" LOC=P32, P33, P34
#
# -----------------------
# Place a logic element(called a BEL) in a specific CLB location.  BEL = FF, LUT, RAM, etc...
# -----------------------
#INST instance_path/BEL_inst_name  LOC = CLB_R17C36
#
# -----------------------
# Place CLB in rectangular area from CLB R1C1 to CLB R5C7
# -----------------------
#INST /U1/U2/reg<0> LOC=clb_r1c1:clb_r5c7
#
# -----------------------
# Place Heirarchial logic block in rectangular area from CLB R1C1 to CLB R5C7
# -----------------------
#INST /U1* LOC=clb_r1c1:clb_r5c7
#
# -----------------------
# Prohibit IO pin P26 or CLBR5C3 from being used:
# -----------------------
#CONFIG PROHIBIT = P26
#CONFIG PROHIBIT = CLB_R5C3
# Config Prohibit is very importadatant for frocing the software to not use critical
# configuration pins like INIT or DOUT on the FPGA.  The Mode pins and JTAG
# Pins require a special pad so they will not be availabe to this constraINT
#
# -----------------------
# Assign an OBUF to be FAST or SLOW:
# -----------------------
#INST obuf_instance_name FAST
#INST obuf_instance_name SLOW
#
# -----------------------
# FPGAs only:  IOB input Flip-flop delay specifcation
# -----------------------
# Declare an IOB input FF delay (default = MAXDELAY).
# NOTE:  MEDDELAY/NODELAY can be attached to a CLB FF that is pushed
# INTo an IOB by the "map -pr i" option.
#INST input_ff_instance_name MEDDELAY
#INST input_ff_instance_name NODELAY
#
# -----------------------
# Assign Global Clock Buffers Lower Left Right Side
# -----------------------
# INST gbuf1 LOC=SSW
#
# #

NET "LCLK" TNM_NET = "LCLK";
TIMESPEC "TS_LCLK" = PERIOD "LCLK" 15 NS HIGH 50 %;
TIMESPEC "TS_P2P" = FROM "PADS" TO "PADS" 25 NS;
OFFSET = OUT 22 NS AFTER "LCLK";
#PACE: START OF CONSTRAINTS GENERATED BY PACE

#PACE: START OF PACE I/O PIN ASSIGNMENTS
NET "A<0>"  LOC = "P87" | SLEW = SLOW  | IOSTANDARD = LVTTL ;
NET "A<1>"  LOC = "P94" | SLEW = SLOW  | IOSTANDARD = LVTTL ;
NET "A<2>"  LOC = "P46" | SLEW = SLOW  | IOSTANDARD = LVTTL ;
NET "A<3>"  LOC = "P57" | SLEW = SLOW  | IOSTANDARD = LVTTL ;
NET "A<4>"  LOC = "P86" | IOSTANDARD = LVTTL ;
NET "A<5>"  LOC = "P90" | IOSTANDARD = LVTTL ;
NET "A<6>"  LOC = "P45" | IOSTANDARD = LVTTL ;
NET "A<7>"  LOC = "P49" | IOSTANDARD = LVTTL ;
NET "ADS"  LOC = "P98" | IOSTANDARD = LVTTL ;
NET "B<0>"  LOC = "P89" | SLEW = SLOW  | IOSTANDARD = LVTTL ;
NET "B<1>"  LOC = "P96" | SLEW = SLOW  | IOSTANDARD = LVTTL ;
NET "B<2>"  LOC = "P48" | SLEW = SLOW  | IOSTANDARD = LVTTL ;
NET "B<3>"  LOC = "P59" | SLEW = SLOW  | IOSTANDARD = LVTTL ;
NET "B<4>"  LOC = "P88" | IOSTANDARD = LVTTL ;
NET "B<5>"  LOC = "P95" | IOSTANDARD = LVTTL ;
NET "B<6>"  LOC = "P47" | IOSTANDARD = LVTTL ;
NET "B<7>"  LOC = "P58" | IOSTANDARD = LVTTL ;
NET "DIR<0>"  LOC = "P68" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "DIR<1>"  LOC = "P70" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "DIR<2>"  LOC = "P30" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "DIR<3>"  LOC = "P33" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "DIR<4>"  LOC = "P67" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "DIR<5>"  LOC = "P69" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "DIR<6>"  LOC = "P29" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "DIR<7>"  LOC = "P31" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "ENA<0>"  LOC = "P61" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "ENA<1>"  LOC = "P63" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "ENA<2>"  LOC = "P23" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "ENA<3>"  LOC = "P27" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "ENA<4>"  LOC = "P60" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "ENA<5>"  LOC = "P62" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "ENA<6>"  LOC = "P22" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "ENA<7>"  LOC = "P24" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "IDX<0>"  LOC = "P82" | SLEW = SLOW  | IOSTANDARD = LVTTL ;
NET "IDX<1>"  LOC = "P84" | SLEW = SLOW  | IOSTANDARD = LVTTL ;
NET "IDX<2>"  LOC = "P42" | SLEW = SLOW  | IOSTANDARD = LVTTL ;
NET "IDX<3>"  LOC = "P44" | SLEW = SLOW  | IOSTANDARD = LVTTL ;
NET "IDX<4>"  LOC = "P81" | IOSTANDARD = LVTTL ;
NET "IDX<5>"  LOC = "P83" | IOSTANDARD = LVTTL ;
NET "IDX<6>"  LOC = "P41" | IOSTANDARD = LVTTL ;
NET "IDX<7>"  LOC = "P43" | IOSTANDARD = LVTTL ;
NET "INT"  LOC = "P112" | SLEW = SLOW  | DRIVE = 24  | IOSTANDARD = LVTTL ;
NET "IOBITSA<0>"  LOC = "P181" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<10>"  LOC = "P200" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<11>"  LOC = "P201" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<12>"  LOC = "P202" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<13>"  LOC = "P203" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<14>"  LOC = "P204" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<15>"  LOC = "P205" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<16>"  LOC = "P206" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<17>"  LOC = "P3" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<18>"  LOC = "P4" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<19>"  LOC = "P5" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<1>"  LOC = "P187" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<20>"  LOC = "P6" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<21>"  LOC = "P7" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<22>"  LOC = "P8" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<23>"  LOC = "P9" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<2>"  LOC = "P188" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<3>"  LOC = "P189" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<4>"  LOC = "P191" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<5>"  LOC = "P192" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<6>"  LOC = "P193" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<7>"  LOC = "P194" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<8>"  LOC = "P195" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "IOBITSA<9>"  LOC = "P199" | IOSTANDARD = LVTTL  | DRIVE = 24  | SLEW = SLOW ;
NET "LAD<0>"  LOC = "P153" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<10>"  LOC = "P172" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<11>"  LOC = "P168" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<12>"  LOC = "P167" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<13>"  LOC = "P166" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<14>"  LOC = "P165" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<15>"  LOC = "P164" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<16>"  LOC = "P163" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<17>"  LOC = "P162" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<18>"  LOC = "P152" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<19>"  LOC = "P151" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<1>"  LOC = "P146" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<20>"  LOC = "P150" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<21>"  LOC = "P149" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<22>"  LOC = "P148" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<23>"  LOC = "P147" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<24>"  LOC = "P141" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<25>"  LOC = "P140" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<26>"  LOC = "P139" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<27>"  LOC = "P138" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<28>"  LOC = "P136" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<29>"  LOC = "P134" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<2>"  LOC = "P142" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<30>"  LOC = "P133" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<31>"  LOC = "P132" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = FAST ;
NET "LAD<3>"  LOC = "P135" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<4>"  LOC = "P126" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<5>"  LOC = "P119" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<6>"  LOC = "P115" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<7>"  LOC = "P108" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<8>"  LOC = "P174" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LAD<9>"  LOC = "P173" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 8 ;
NET "LCLK"  LOC = "P182" | IOSTANDARD = LVTTL ;
NET "LEDS<0>"  LOC = "P10" | SLEW = SLOW  | DRIVE = 24  | IOSTANDARD = LVTTL ;
NET "LEDS<1>"  LOC = "P14" | SLEW = SLOW  | DRIVE = 24  | IOSTANDARD = LVTTL ;
NET "LEDS<2>"  LOC = "P15" | SLEW = SLOW  | DRIVE = 24  | IOSTANDARD = LVTTL ;
NET "LEDS<3>"  LOC = "P16" | SLEW = SLOW  | DRIVE = 24  | IOSTANDARD = LVTTL ;
NET "LEDS<4>"  LOC = "P17" | SLEW = SLOW  | DRIVE = 24  | IOSTANDARD = LVTTL ;
NET "LEDS<5>"  LOC = "P18" | SLEW = SLOW  | DRIVE = 24  | IOSTANDARD = LVTTL ;
NET "LEDS<6>"  LOC = "P20" | SLEW = SLOW  | DRIVE = 24  | IOSTANDARD = LVTTL ;
NET "LEDS<7>"  LOC = "P21" | SLEW = SLOW  | DRIVE = 24  | IOSTANDARD = LVTTL ;
NET "LRD"  LOC = "P100" | IOSTANDARD = LVTTL ;
NET "LW_R"  LOC = "P101" | IOSTANDARD = LVTTL ;
NET "LWR"  LOC = "P160" | IOSTANDARD = LVTTL ;
NET "PWM<0>"  LOC = "P73" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "PWM<1>"  LOC = "P75" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "PWM<2>"  LOC = "P35" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "PWM<3>"  LOC = "P37" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "PWM<4>"  LOC = "P71" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "PWM<5>"  LOC = "P74" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "PWM<6>"  LOC = "P34" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "PWM<7>"  LOC = "P36" | SLEW = SLOW  | IOSTANDARD = LVTTL  | DRIVE = 24 ;
NET "READY"  LOC = "P102" | SLEW = FAST  | IOSTANDARD = LVTTL  | DRIVE = 24 ;

#PACE: START OF PACE AREA CONSTRAINTS

#PACE: START OF PACE PROHIBIT CONSTRAINTS

#PACE: END OF CONSTRAINTS GENERATED BY PACE