8 channel HOSTMOT-E config register map: 32 bit base offsets: Counter0 0x00 Counter1 0x04 Counter2 0x08 Counter3 0x0C Counter4 0x10 Counter5 0x14 Counter6 0x18 Counter7 0x1C SecCounter0 0x20 SecCounter1 0x24 SecCounter2 0x28 SecCounter3 0x2C (0x30 .. 0x3F unused) I/O port: PORTA 0xA0 24 bit I/O port PORTADDR 0xA4 24 I/O port Data direction register - 1 = out IDREG 0xD0 IDREG identifies hostmot configuration and revision = 0xAARR00NN 0xAA MS byte is constant for probe, RR is 8 bit revision number 0x00 is constant for probe and NN is number of Axis MasterClock 0xD4 MasterClock is 32 bit master clock frequency in Hz. 16 bit base offsets: CCR0 0x40 CCR1 0x42 CCR2 0x44 CCR3 0x46 CCR4 0x48 CCR5 0x4A CCR6 0x4C CCR7 0x4E SecCCR0 0x50 SecCCR1 0x52 SecCCR2 0x54 SecCCR3 0x56 CCR (Counter Control Register) Bit definitions: BIT15 IndexMaskPol 0 = IM is active low 1 = IM is active high BIT14 IndexMaskEnable 0 = IM is dont-care 1 = IM must be true to detect index ( bit 14 read back is real time index mask status) BIT13 LatchOnce if 1, clear LOI (bit 12) when index detected BIT12 LatchOnIndex 0 = no LOI 1 = latch counter on index BIT11 AutoCount 0 = normal operation 1 = counter counts up at PCI clk rate BIT10 CounterMode 0 = quadrature 1 = up/down BIT9 QuadFilter 0 = ~11 Mhz filter 1 = ~4 MHz filter BIT8 LocalHold 1 = hold counter 1 = counter can count BIT7 Indexgate 0 = index anytime 1 = index detected only when A=B=0 BIT6 ClearOnce if 1, clear COI (bit5) when index detected BIT5 ClearOnIndex 0 = no COI 1 = clear counter on index BIT4 IndexPol 0 = active low index 1 = active high index BIT3 LatchOnRead 1 = latch on read (Transparent mode) BIT2 LocalClear Real time index status (reads) counter clear (writes) BIT1 B Real time input A status (read only) BIT0 A Read time input B status (read only) (0x58 .. 0x5F unused) PWMVAL0 0x60 PWMVAL1 0x62 PWMVAL2 0x64 PWMVAL3 0x66 PWMVAL4 0x68 PWMVAL5 0x6A PWMVAL6 0x6C PWMVAL7 0x6E (0x78 .. 0x7F unused) In signed mode, PWMVAL is a signed 16 bit number which is output as 10 bit PWM plus sign on the direction bit. In unsignedmode PWMVAL is an unsigned 16 bit number which is output as 10 bit PWM. DIR is an input in unsigned mode. PCR0 0x80 PCR1 0x82 PCR2 0x84 PCR3 0x86 PCR4 0x88 PCR5 0x8A PCR6 0x8C PCR7 0x8E (0x98 .. 0x9F unused) PCR bit Definitions: BIT4 DIR bit (input if in unsigned mode) BIT3 Realtime PWM output bit status (read only) BIT2 unsigned mode bit 1 = unsigned BIT1 Interlace enable (interlaces PWM output for use as analog out) BIT0 Enable -- enables PWM and ENA bit if set GContReg 0xC0 GContReg bit definitions: BIT4 0 = NOP 1 = Reload WD timer BIT3 0 = NOP 1 = Clear IRQ BIT2 0 = NOP 1 = Clear all PWMs BIT1 0 = NOP 1 = Latch all counters BIT0 0 = NOP 1 = Clear all counters Note GContReg is write only and "transient" you only need to write once to accomplish the desired action, no need to clear the bit later... GModeReg 0xC2 GMode register bit definitions: BIT7 SOT Stop on watchdog timeout control bit BIT6 IRQstatus Real time IRQ status BIT5 IRQMask IRQ mask bit BIT4 MissedIRQ Missed interrupt status BIT3 SOM Stop on Missed interrupt control bit BIT2 LOI Latch on interrupt control bit BIT1 PWMEN Global PWM enable BIT0 CTREN Global counter enable IRQDivSel 0xC4 8 bit programmable divider for IRQ rate = PWM rate/(IRQDivSel+1) RATE register 0xC6 16 bit rate register: multiplies PWM reference counter input rate by RATE/65536 so final PWM rate = MasterClock/1024 * RATE/65536 WDTimeOut 0xC8 R/W 16 bit watchdog timeout register, sets watchdog timeout in ~1 usec increments (PCICLK/33) WDtimer register is loaded with this value when bit 4 of gcontreg is set WDTimer 0xCA R/O timer register displays ~usec until watchdog bytes LEDView 0xCC LED view register determines what channel the on card LEDS monitor. LEDs monitor the following signals of the selected channel: CR1 IRQLatch CR2 QuadA CR3 QuadB CR4 IDX CR5 DIR CR6 PWM CR7 ENA CR8 WDTIMEOUT