JDF G
// Created by Project Navigator ver 1.0
PROJECT Untitled
DESIGN hostmot5-8ehtest
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s200
DEVICETIME 1068164700
DEVPKG pq208
DEVPKGTIME 315558000
DEVSPEED -5
DEVSPEEDTIME 315558000
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE indexreg.vhd
SOURCE gcontreg.vhd
SOURCE gmodereg.vhd
SOURCE word24rb.vhd
SOURCE wordpr24.vhd
SOURCE threeph.vhd
SOURCE fcounter.vhd
SOURCE timeout.vhd
SOURCE sinetab.xco
SOURCE new3phf.vhd
SOURCE fifomem32.xco
SOURCE fifomem.xco
SOURCE new3phd.vhd
SOURCE countere.vhd
SOURCE hostmot5-8eh.vhd
SOURCE idreadback.vhd
SOURCE pwmrefh.vhd
SOURCE pwmgenh.vhd
DEPASSOC hostmot5_8eh hostmot5-8eh.ucf
[Normal]
p_ModelSimSimRunTime_tbw=xstvhd, spartan2, Bencher Waveform.t_MSimulateBehavioralVhdlModel, 315558000, 1000ns
p_xstEquivRegRemoval=xstvhd, spartan2, Schematic.t_synthesize, 1123701967, True
p_xstGenerateRTLNetlist=xstvhd, spartan2, Schematic.t_synthesize, 1123548191, No
p_xstOptimizeInsPrimtives=xstvhd, spartan2, Schematic.t_synthesize, 1123701967, True
xilxMapReportDetail=xstvhd, spartan2, Implementation.t_placeAndRouteDes, 1068244222, True
xilxPAReffortLevel=xstvhd, spartan2, Implementation.t_placeAndRouteDes, 1126567772, Standard
xilxPreTrceRptLimit=xstvhd, spartan2, Implementation.t_placeAndRouteDes, 1068244222, 500
xilxPreTrceRptTiming=xstvhd, spartan2, Implementation.t_placeAndRouteDes, 1068244222, 500
xilxSynthGlobOpt=xstvhd, spartan2, Schematic.t_synthesize, 1126567806, Offset Out After
xilxSynthMaxFanout=xstvhd, spartan2, Schematic.t_synthesize, 1126568302, 20
_SynthOptEffort=xstvhd, spartan2, Schematic.t_synthesize, 1123701967, High
[STATUS-ALL]
hostmot5_8eh.ncdFile=WARNINGS,1167425711
hostmot5_8eh.ngcFile=WARNINGS,1167425619
[STRATEGY-LIST]
Normal=True